Method and apparatus for flip-chip packaging providing testing capability

ABSTRACT

A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface thereof, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip chip semiconductor device assembly.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of application Ser. No. 10/150,892,filed May 17, 2002, pending, which is related to U.S. patent applicationSer. No. 09/944,465 filed Aug. 30,2001 and entitled MICROELECTRONICDEVICES AND METHODS OF MANUFACTURE, and to the following U.S. patentapplications filed on even date therewith: Ser. No. 10/150,893 (AttorneyDocket No. 4812US), entitled INTERPOSER CONFIGURED TO REDUCE THEPROFILES OF SEMICONDUCTOR DEVICE ASSEMBLIES AND PACKAGES INCLUDING THESAME AND METHODS; Ser. No. 10/150,516 (Attorney Docket No. 4878US),entitled SEMICONDUCTOR DIE PACKAGES WITH RECESSED INTERCONNECTINGSTRUCTURES AND METHODS FOR ASSEMBLING THE SAME; Ser. No. 10/150,653(Attorney Docket No. 4879US), entitled FLIP CHIP PACKAGING USINGRECESSED INTERPOSER TERMINALS; Ser. No. 10/150,902 (Attorney Docket No.4973US), entitled METHOD AND APPARATUS FOR DIELECTRIC FILLING OF FLIPCHIP ON INTERPOSER ASSEMBLY; and Ser. No. 10/150,901 (Attorney DocketNo. 4974US), entitled METHODS FOR ASSEMBLY AND PACKAGING OF FLIP CHIPCONFIGURED DICE WITH INTERPOSER.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to packaging of semiconductordice and, more specifically, to packaging of flip-chip configuredsemiconductor dice employing an interposer substrate having recesses inone or both sides thereof for receiving discrete conductive elementsprojecting from the semiconductor dice.

2. State of the Art

Chip-On-Board (“COB”) or Board-On-Chip (“BOC”) technology is used toattach a semiconductor die directly to a carrier substrate such as aprinted circuit board (“PCB”), or an interposer may be employed andattachment may be effected using flip chip attachment, wire bonding, ortape automated bonding (“TAB”).

Flip chip attachment generally includes electrically and mechanicallyattaching a semiconductor die by its active surface to an interposer orother carrier substrate using a pattern of discrete conductive elementstherebetween. The discrete conductive elements are generally disposed onthe active surface of the die during fabrication thereof, but mayinstead be disposed on the carrier substrate. The discrete conductiveelements may comprise minute conductive bumps, balls or columns ofvarious configurations. Each discrete conductive element is placedcorresponding to mutually aligned locations of bond pads (or other I/Olocations) on the semiconductor die and terminals on the carriersubstrate when the two components are superimposed. The semiconductordie is thus electrically and mechanically connected to the carriersubstrate by, for example, reflowing conductive bumps of solder orcuring conductive or conductor-filled epoxy bumps. A dielectricunderfill may then be disposed between the die and the carrier substratefor environmental protection and to enhance the mechanical attachment ofthe die to the carrier substrate.

Wire bonding and TAB attachment techniques generally begin withattaching a semiconductor die by its back side to the surface of acarrier substrate with an appropriate adhesive, such as an epoxy orsilver solder. In wire bonding, a plurality of fine wires is discretelyattached to bond pads on the semiconductor die and then extended andbonded to corresponding terminal pads on the carrier substrate. Adielectric encapsulant such as a silicone or epoxy may then be appliedto protect the fine wires and bond sites. In TAB, ends of metal tracescarried on a flexible insulating tape such as a polyimide are attached,as by thermocompression bonding, directly to the bond pads on thesemiconductor die and corresponding terminal pads on the carriersubstrate.

Higher performance, lower cost, increased miniaturization of components,and greater packaging density of integrated circuits are ongoing goalsof the computer industry. As new generations of integrated circuitproducts are released, the number of components used to fabricate themtends to decrease due to advances in technology even though thefunctionality of the products increase. For example, on the average,there is approximately a ten percent decrease in components for everyproduct generation over the previous generation having equivalentfunctionality.

Recent trends in packaging are moving with increasing rapidity towardflip chip attachment due to improved electrical performance and greaterpackaging density. However, flip chip attachment is not withoutproblems, such as the high cost for a third metal reroute of bond padsfrom the middle or periphery of a die to a two-dimensional array which,in turn, may result in overlong and unequal length electrical paths. Inaddition, many conventional flip chip techniques exhibit a lack ofconsistent reliability of the interconnections between the chip and theinterposer or other carrier substrate as a result of the increasedminiaturization as well as difficulties in mutual alignment of the dieand carrier substrate to effect such interconnections. Effectivererouting of bond pads may also be limited by die size. Anotherhindrance to flip chip packaging has been difficulty in electricallytesting completed flip chip semiconductor device assemblies usingexisting test probe equipment. Thus, even if a semiconductor die in theassembly is a so-called “known good die,” the assembly itself mayexhibit defects which are not easily detected and which may, even ifdetected, be at a stage in the fabrication process subsequent toencapsulation, rendering rework of the assembly difficult if notimpossible.

Further, flip chip packages for a bumped semiconductor die employing aninterposer may be undesirably thick due to the combined height of thedie and interposer. This is due to the use in conventional packagingtechniques of relatively costly interposers comprising dual conductivelayers having a dielectric member sandwiched therebetween, the bumpedsemiconductor die resting on and connected to traces of the conductivelayer on one side of the interposer and electrically connected to tracesof the conductive layer on the opposing side, conductive vias extendingtherebetween. Finally, underfilling a flip chip-attached semiconductordie to a carrier substrate with dielectric filler material can be alengthy and often unreliable process, and the presence of the underfillmakes reworking of defective assemblies difficult if not impossible.

Other difficulties with conventional packages include an inability toaccommodate die size reductions, or “shrinks,” as a given designprogresses through several generations without developing new interposerdesigns and tooling. As more functionality is included in dice,necessitating a greater number of inputs and outputs (I/Os), decreasedspacing or pitch between the I/Os places severe limitations on the useof conventional interposers. In addition, with conventional packages, adie is not tested until package assembly is complete, resulting inexcess cost since a defective die or die and interposer assembly is notdetected until the package is finished.

For example, U.S. Pat. No. 5,710,071 to Beddingfield et al. discloses afairly typical flip chip attachment of a semiconductor die to asubstrate and a method of underfilling a gap between the semiconductordie and substrate. In particular, the semiconductor die is attachedfacedown to the substrate, wherein conductive bumps on the die aredirectly bonded to bond pads on the upper surface of the substrate,which provides the gap between the die and substrate. The underfillmaterial flows through the gap between the semiconductor die and thesubstrate via capillary action toward an aperture in the substrate,thereby expelling air in the gap through the aperture in the substratein an effort to minimize voids in the underfill material. However, suchan underfilling method still is unnecessarily time consuming due tohaving to underfill the entire semiconductor die. Further, the flip chipattachment technique disclosed in U.S. Pat. No. 5,710,071 exhibitsdifficulties in aligning the conductive bumps with the bond pads on thesubstrate and requires the expense of having a third metal reroute inthe substrate.

Therefore, it would be advantageous to improve the reliability ofinterconnections between a chip and a carrier substrate such as aninterposer by achieving accurate alignment of the interconnections, animproved underfill process, and the elimination of the necessity for athird metal reroute, while reducing total assembly height in combinationwith the ability to employ commercially available, widely practicedsemiconductor device fabrication techniques and materials as well asexisting test equipment.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to methods and apparatus for assembling,testing and packaging individual and multiple semiconductor dice with aninterposer substrate in a flip chip-type arrangement and, further, thepresent invention relates to an interposer substrate having multiplerecess patterns for mounting semiconductor dice with differently spacedand sized conductive bump configurations. The present invention providesa flip chip semiconductor device assembly substantially reduced inheight or thickness and with improved mechanical and electricalreliability of the interconnections between a semiconductor die and acarrier substrate in comparison to conventional flip chip assemblies,while also improving the alignment capability of attaching thesemiconductor die to the interposer substrate. The present inventionalso eliminates the requirement of a third metal reroute necessitated inmost flip chip assemblies and eliminates the need for underfilling orreduces the time for underfilling if optionally effected. In addition,the present invention facilitates relatively simple and efficienttesting of the semiconductor assembly.

The flip chip semiconductor device assembly of the present inventionincludes an interposer substrate having a first surface and a secondsurface, wherein at least one of the first surface and the secondsurface includes multiple recesses formed therein and arranged in atleast two different recess patterns for attaching one or moreconductively bumped semiconductor dice thereto. The one or moreconductively bumped semiconductor dice may be assembled face (or activesurface) down to the interposer substrate in a flip chip-typearrangement so that the conductive bumps of the semiconductor die ordice are disposed in a corresponding recess pattern. Conductive elementsin the recesses are interconnected by traces to test pads that areexposed proximate a periphery on at least one of the first and secondsurfaces of the interposer substrate. Such test pads allow easy accessfor probe testing the electrical integrity of the one or moresemiconductor dice mounted to the interposer substrate.

In this manner, the recesses of the at least two different recesspatterns are spaced, sized and configured to substantially receive theconductive bumps on the conductively bumped semiconductor die or dice toan extent so that an active surface of each semiconductor die liesimmediately adjacent a surface of the interposer substrate. An adhesiveelement in the form of a liquid or gel adhesive or an adhesive-coatedtape may optionally be disposed between the semiconductor die andadjacent interposer substrate surface. As such, there is a reduction inthe height of the flip chip assembly due to the conductive bumps beingsubstantially or even completely received in the recesses, which allowsfor the conductive bumps on the die to be formed larger for increasedreliability without increasing the height of the flip chip assemblywhile also removing the need for a third metal reroute on thesemiconductor die. Furthermore, such a flip chip semiconductor deviceassembly may eliminate the need for underfilling between a semiconductordie and the interposer substrate. If underfilling is employed, thepresent invention reduces the time for underfilling the assembly andamount of dielectric filler required, since any space in a recessproximate a conductive bump is minimal and vertical space, or standoff,between the semiconductor die and adjacent interposer substrate surfaceis at least reduced and, in some, instances greatly reduced due to thepresence of the adhesive element.

In a first embodiment, the interposer substrate includes multiplerecesses formed in a first recess pattern on the first surface thereofand a second recess pattern on the second surface thereof. The first andsecond recess patterns are configured such that semiconductor dicehaving differently spaced and arranged conductive bump configurationsthereon (including differently sized semiconductor dice) may each bemounted to the interposer substrate. In this manner, the interposersubstrate of the first embodiment may facilitate mounting twosemiconductor dice thereto by mounting a first die on the first surfaceof the interposer substrate and mounting a second die on the secondsurface of the interposer substrate.

In a second embodiment, the interposer substrate includes multiplerecesses formed in a first recess pattern and a second, different recesspattern in the first surface thereof. Such first and second recesspatterns enable semiconductor dice having differently spaced andarranged conductive bump configurations thereon (including differentlysized dice) to be alternatively mounted to a first surface of theinterposer substrate. In this manner, the interposer substrate of thesecond embodiment facilitates the option of mounting differently sizeddice and/or semiconductor dice having differently spaced conductive bumpconfigurations.

In a third embodiment, the interposer substrate includes multiplerecesses formed in a first recess pattern and a second, different recesspattern on the first surface of the interposer substrate and a thirdrecess pattern and a fourth, different recess pattern on the secondsurface of the interposer substrate. The first and second recesspatterns are configured so that semiconductor dice having differentlyspaced and arranged conductive bump configurations thereon (includingdifferently sized semiconductor dice) may be optionally mounted to afirst surface of the interposer substrate and the third and fourthrecess patterns are configured so that semiconductor dice havingdifferently spaced and arranged conductive bump configurations thereon(including differently sized semiconductor dice) may be optionallymounted to a second surface of the interposer substrate. In this manner,the interposer substrate of the third embodiment facilitates the optionof mounting differently sized dice and/or semiconductor dice havingdifferently spaced conductive bump configurations on both the firstsurface and the second surface of the interposer substrate.

In a fourth embodiment, the interposer substrate includes multiplerecesses formed in first, second, third and fourth different recesspatterns in the first surface of the interposer substrate. Such recesspatterns each are configured and sized so that semiconductor dice havingdifferently spaced conductive bump configurations thereon (includingdifferently sized semiconductor dice) may be optionally mounted to afirst surface of the interposer substrate. Thus, the interposersubstrate of the fourth embodiment facilitates the option of mountingdifferently sized dice and/or semiconductor dice having differentlyspaced conductive bump configurations on the first surface of theinterposer substrate.

The recess patterns referred to in the interposer substrate of theprevious embodiments may be staggered and/or aligned with respect toeach other. Also, the recess patterns may include some recess patternsthat are staggered with respect to each other and some recess patternsthat are aligned with respect to each other.

Turning to another aspect of the present invention, the conductive bumpsutilized for interconnecting the semiconductor die and the interposersubstrate may be bonded to conductive elements in the recesses byreflowing the conductive bumps, curing the conductive bumps, ultrasonicbonding, or thermal compression, depending upon the bump materialemployed. In addition, nonsolid conductive material such as a conductivepaste may be provided on the conductive bumps or within the recessesprior to disposing the conductive bumps in the recesses. Alternatively,unattached conductive bumps may be provided in the conductive paste inthe recesses, after which, the die may be aligned and attached to theconductive bumps. As such, in addition to providing a more reliableelectrical connection between the conductive bumps and the conductiveinterconnect, the conductive paste compensates for any noncoplanaritydue to various conductive bump sizes, recess depths and planarityvariation in the surfaces of the semiconductor die and interposersubstrate. The adhesive element, as previously mentioned, on the firstsurface and/or the second surface of the interposer substrate may alsocompensate and act as a height controller for any irregularities in thecoplanarity between a semiconductor die and the interposer substrate.

The flip chip semiconductor device assembly of the present invention mayalso include relatively large solder balls or other conductive elementsattached to a surface of the interposer substrate, interconnecting withthe conductive elements and the conductive bumps of the semiconductordie. The solder balls act as interconnects to another substrate, such asa printed circuit board. The flip chip semiconductor device assembly mayalso be fully or partially encapsulated by an encapsulation material orthe semiconductor die or dice may be left exposed.

The flip chip semiconductor device assembly of the present invention mayalso be assembled at a wafer level, wherein a wafer scale interposersubstrate includes at least two different recess patterns. As such, thewafer scale interposer substrate may facilitate assembly with differentwafers having different conductive bump configurations which correspondwith the at least two different recess patterns in the wafer scaleinterposer substrate. In this manner, optional wafers with differentconductive bump configurations may be attached facedown to theinterposer substrate with conductive bumps on the wafer disposed andsubmerged in recesses formed in the wafer scale interposer substrate.The wafer and wafer scale interposer substrate may then be singulated ordiced into individual flip chip semiconductor device assemblies. Partialencapsulation of these assemblies may be performed at the wafer leveland optionally completed subsequent to being diced into individual flipchip semiconductor device assemblies.

The interposer substrate may be fabricated from a flexible, tape-likematerial including at least one flexible dielectric member and at leastone conductive member laminated thereto. The at least one flexibledielectric member may include a polyimide layer. The at least oneconductive member is patterned into traces by etching or printingconductive ink and may include conductive elements at recess locationsin the form of conductive pads linked by the conductive traces to testpads and other conductive pads for external connection of the assemblyto other like assemblies or to higher-level packaging. The multiplerecesses are formed in at least one of the first and second surfaces ofthe at least one flexible dielectric member by etching, mechanicaldrilling or punching or laser ablation, wherein each of the recessesextends at least to a portion of a conductive element and is sized andconfigured to receive the conductive bumps on the semiconductor die. Theinterposer substrate of the present invention may also be formed ofother interposer substrate materials, including nonflexible materials,such as a BT resin, FR4, FR5 and ceramics.

The interposer substrate may comprise a single flexible dielectricmember having conductive layers comprising conductive traces on opposingsides thereof or may comprise a single conductive layer laminatedbetween two dielectric members. In either instance, recesses may extendfrom either side of the interposer substrate through a dielectric memberto expose portions of conductive elements.

In another aspect of the present invention, the flip chip semiconductordevice assembly is mounted to a circuit board in a computer or acomputer system. In the computer system, the circuit board iselectrically connected to a processor device which electricallycommunicates with an input device and an output device.

Other features and advantages of the present invention will becomeapparent to those of skill in the art through a consideration of theensuing description, the accompanying drawings and the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing outand distinctly claiming that which is regarded as the present invention,the advantages of this invention may be ascertained from the followingdescription of the invention when read in conjunction with theaccompanying drawings, wherein:

FIG. 1 is a simplified top view of a first embodiment of an interposersubstrate illustrating a first recess pattern and a second, differentrecess pattern (shown in broken lines) formed in the interposersubstrate according to the present invention;

FIG. 2 is a simplified cross-sectional side view taken along line 2-2 inFIG. 1, illustrating multiple recesses in a first surface and a secondsurface of the interposer substrate according to the present invention;

FIG. 3 illustrates mounting a first die and a second die facedown torespective first and second surfaces of the interposer substrate to forma flip chip semiconductor device assembly, according to the presentinvention;

FIG. 4 illustrates applying dielectric filler material to the flip chipsemiconductor device assembly according to the present invention;

FIG. 5 illustrates testing the flip chip semiconductor device assemblyaccording to the present invention;

FIG. 6 illustrates mounting a flip chip semiconductor device assemblyaccording to the present invention to another substrate with conductiveelements therebetween;

FIG. 7 illustrates applying encapsulation material with a dispenser andencapsulation member to the semiconductor device assembly according tothe present invention mounted to another substrate as shown in FIG. 6;

FIG. 8 illustrates a fully encapsulated flip chip semiconductor deviceassembly mounted to another substrate as shown in FIG. 6;

FIG. 9 is a simplified top view of a second embodiment of an interposersubstrate according to the present invention, illustrating a firstrecess pattern and a second, different recess pattern formed in the samesurface of the interposer substrate;

FIG. 10 is a simplified cross-sectional side view taken along line 10-10in FIG. 9;

FIG. 11 is a simplified cross-sectional side view of a semiconductor diemounted facedown to an interposer substrate with conductive bumpsdisposed in one of the first recess pattern and the second recesspattern to form a flip chip semiconductor device assembly according tothe present invention under test;

FIG. 12 is a simplified cross-sectional side view of multiple flip chipsemiconductor device assemblies of the second embodiment attached withconductive elements extending therebetween with the bottom interposersubstrate attached to another substrate, according to the presentinvention;

FIG. 13 is a simplified top view of a third embodiment of an interposersubstrate, illustrating first, second, third (shown in broken lines) andfourth (shown in broken lines) recess patterns formed in the interposersubstrate, according to the present invention;

FIG. 14 is a simplified top view of a fourth embodiment of an interposersubstrate, illustrating first, second, third and fourth different recesspatterns formed in a first surface of an interposer substrate, accordingto the present invention;

FIG. 15 is a simplified block diagram of the semiconductor assembly ofthe present invention integrated in a computer system;

FIG. 16 is a simplified cross-sectional side view of a fifth embodimentof a semiconductor device assembly according to the present invention;and

FIG. 17 is a simplified side view of a sixth embodiment of asemiconductor device assembly according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be hereinafter described withreference to the accompanying drawings. It would be understood thatthese illustrations are not to be taken as actual views of any specificapparatus or method of the present invention, but are merely exemplary,idealized representations employed to more clearly and fully depict thepresent invention than might otherwise be possible. Additionally,elements and features common between the drawing figures retain the samenumerical designation.

FIGS. 1 and 2 depict a first embodiment of an interposer substrate 110of the present invention, wherein FIG. 1 illustrates a simplified topplan view of interposer substrate 110 and FIG. 2 illustrates asimplified cross-sectional view of interposer substrate 110 taken alongline 2-2 in FIG. 1. Interposer substrate 110 includes a first surface112 and a second surface 114, wherein each surface may include multiplerecesses 120 formed therein and respective first and second die attachsites 142 and 144, respective first and second adhesive elements 152 and154 provided on the respective first and second die attach sites 142 and144, and test pads 134 exposed proximate a periphery 116 of theinterposer substrate 110.

Interposer substrate 110 is preferably, but not limited to, a flexiblesubstrate, wherein interposer substrate 110 may include a dielectricmember 136 disposed between conductive layers, each comprising aplurality of conductive elements configured as traces 130. Thedielectric member 136 may be formed from any known substrate materialand is preferably formed of, by way of example, a flexible laminatedpolymer or polyimide layer, such as UPILEX®, produced by Ube Industries,Ltd., or any other polymer-type layer. The interposer substrate 110 mayalso be made of a bismaleimide triazine (BT) resin, FR 4, FR 5 or anytype of substantially flexible material or nonflexible material, such asa ceramic or epoxy resin.

The conductive layers are preferably formed of copper, or a copperalloy, but may be any suitable electrically conductive material. Theconductive layers may include traces 130 extending to conductive pads132 for connection to conductive bumps of a semiconductor die andconductive pads 133 for use in externally connecting the interposersubstrate 110 and test pads 134 for electrical testing of the interposersubstrate 110 with one or more semiconductor dice connected thereto.Such traces 130 may be formed subtractively as by masking and etching aconductive layer, additively by printing with conductive ink, or byutilizing any suitable method known in the art. Once the traces 130 arepatterned, a protective solder mask 138 may be formed and patterned overthe traces 130, leaving conductive pads 133 exposed for formation ofconductive bumps such as solder balls thereon. As implied above, theconductive traces, which may, for example, comprise copper or a copperalloy, may be adhered to the dielectric substrate member of UPILEX®, BTresin, FR 4 or, FR 5 laminate material, or other substrate materials,using adhesives as known in the art.

According to the first embodiment of the present invention, the firstsurface 112 and the second surface 114 of interposer substrate 110 eachinclude multiple recesses 120 or vias formed therein in a preselectedpattern and a predetermined sizing. Such recesses 120 may be formed bypatterning, utilizing a chemical wet etch or dry etch, mechanicaldrilling or punching, laser ablation, or any method known in the art andsuitable with the type of materials employed for the interposersubstrate 110. Optionally, the recesses 120 are preferably formed toexpose at least portions of conductive pads 132 of the traces 130, whichmay, in some instances, comprise the trace ends. It is also contemplatedthat electroless plating may, optionally, be formed on walls of therecesses 120.

In this manner, each of the multiple recesses 120 extends to aconductive layer, or more specifically, to the traces 130 or conductivepads 132 defining the conductive layer. The conductive traces 130,conductive pads 132 and conductive pads 133 of a conductive layer on thefirst surface 112 may be interconnected through dielectric member 136 ofinterposer substrate 110 to other conductive traces 130, conductive pads132 or conductive pads 133 on the second surface 114 of interposersubstrate 110 by conductively plated vias 135, as known in the art. Suchconductive pads 133 may be located substantially directly belowconductive pads 132 or, optionally, the conductive pads 133 may be atvarious predetermined locations remote from conductive pads 132 andconnected thereto by the conductive traces 130. The conductive traces130 also extend to test pads 134 proximate the periphery 116 of theinterposer substrate 110, test pads 134 being located on one or bothsurfaces 112 and 114 of interposer substrate 110, as desired. It will beunderstood that elements of the conductive layer on one side ofdielectric member 136 will be offset from those on the other sidethereof in the areas wherein recesses 120 are formed through dielectricmember 136.

Each plurality of recesses 120 in the first surface 112 and the secondsurface 114 of interposer substrate 110 is formed in a preselectedpattern to correspond with a particular bond pad configuration formed onan active surface of a semiconductor die for attaching thereto. Inparticular, the recesses 120 in FIG. 1 are configured in two groups,defining a first recess pattern 122 and a second, different recesspattern 124 (broken lines), each to correspond with a peripheralsemiconductor die bond pad configuration, wherein the first recesspattern 122 may be on the first surface 112 of interposer substrate 110and the second recess pattern 124 may be on the second surface 114 ofinterposer substrate 110. The first recess pattern 122 is depicted toencompass a larger periphery than the second recess pattern 124. Thatis, the recesses 120 of the first recess pattern 122 are closer to aperiphery 116 of interposer substrate 110 than the recesses 120 of thesecond recess pattern 124. Other preselected recess patterns known inthe art and having equal utility in the practice of the presentinvention may, by way of example, include an I-shaped pattern, a singleor double central row recess pattern, or any other recess patternconfigured to correspond and match with any particular semiconductor diebond pad configuration. In addition, the multiple recesses 120themselves may be formed in any suitable shape, such as square,rectangular or circular, and may include tapered sidewalls so that theopenings or mouths of the recesses 120 are larger than the bottomsthereof. Optionally, through the use of conductive vias 135 connectingconductive traces 130 on one surface of interposer substrate 110 withconductive traces on an opposing surface of interposer substrate 110, arecess of the first recess pattern 122 may be electrically connected toa recess of second recess pattern 124 and to a common test pad 134.

FIG. 2 depicts a first adhesive element 152 and a second adhesiveelement 154 disposed on the first surface 112 and the second surface114, respectively, of the interposer substrate 110. The first adhesiveelement 152 and the second adhesive element 154 may be disposed on acenter portion of interposer substrate 110 at respective first andsecond die attach sites 142 and 144 of the respective first and secondsurfaces 112 and 114 of the interposer substrate 110 at a location orlocations on such surfaces unoccupied by the recesses 120. The first andsecond adhesive elements 152 and 154 may comprise any suitable adhesivematerial as known in the art, such as epoxy, acrylic, or a polyimideadhesive. Both the first and second adhesive elements 152 and 154 mayalso comprise, without limitation, a dielectric tape such as a polyimidetape bearing adhesive on both sides thereof with the tape surface facingaway from interposer substrate 110 being covered with a release layeruntil adherence to a semiconductor die is desired. Each of first andsecond adhesive elements 152 and 154 may preferably be, but is notlimited to, about 25 μm in thickness.

Referring to FIG. 3, there is illustrated a first semiconductor die 160and a second semiconductor die 170 mounted facedown to the first surface112 and second surface 114, respectively, of interposer substrate 110 toform a flip chip semiconductor device assembly 180. Semiconductor die160 includes an active surface 162 and a back surface 164, wherein theactive surface 162 includes a plurality of bond pads bearingelectrically conductive bumps 166 thereon. Such conductive bumps 166formed on the first semiconductor die 160 are arranged in aconfiguration wherein the recesses 120 of the first recess pattern 122in the first surface 112 of interposer substrate 110 are sized andarranged to correspond with the bump configuration of the firstsemiconductor die 160 so that the recesses 120 on first surface 112 andthe conductive bumps 166 are a substantially mirror image of each other.Likewise, the second semiconductor die 170 includes an active surface172 and a back surface 174, wherein the active surface 172 includes aplurality of bond pads bearing electrically conductive bumps 176thereon. As with the first semiconductor die 160, the conductive bumps176 formed on the second semiconductor die 170 are arranged in aconfiguration, wherein the recesses 120 of the second recess pattern 124in the second surface 114 of interposer substrate 110 are sized andarranged to correspond with the bump configuration of the secondsemiconductor die 170 so that the recesses 120 on second surface 114 andthe conductive bumps 176 are a substantially mirror image of each other.

Conductive bumps 166 and 176 preferably comprise, but are not limitedto, conductive balls, pillars or columns. The material of conductivebumps 166 and 176 may include, but is not limited to, any known suitablemetals or alloys thereof, such as lead, tin, copper, silver or gold.Conductive or conductor-filled polymers may also be employed, althoughgold and PbSn solder bumps are currently preferred. The conductive bumps166 and 176 may be of uniform characteristics throughout or include, forexample, a core of a first material (including a nonconductive material)having one or more conductive layers of other materials thereon.Conductive bumps 166 and 176 are preferably formed on the active surfaceof each semiconductor die at a wafer level, but such is not required.Conductive bumps 166 and 176 may be formed by metal evaporation,electroplating, stencil printing, gold stud bumping by wire bonders,solder reflow or any suitable method known in the art depending, ofcourse, on the material or materials selected for formation thereof.

As depicted in FIG. 3, interposer substrate 110 is mounted to the firstsemiconductor die 160 and the second semiconductor die 170 to form flipchip semiconductor device assembly 180, wherein such assembly 180provides that each of the first semiconductor die 160 and the secondsemiconductor die 170 and the respective conductive bumps 166 and 176 offirst semiconductor die 160 and second semiconductor die 170 aresubstantially received in a corresponding recess 120 of respective firstrecess pattern 122 and second recess pattern 124 of interposer substrate110 and electrically contact the conductive pads 132 at the bottom ofeach of the recesses 120. The first and second semiconductor dice 160and 170 may be initially attached by the first and second adhesiveelements 152 and 154 on the first and second surfaces 112 and 114,respectively, of the interposer substrate 110. The conductive bumps 166and 176 on the respective first and second semiconductor dice 160 and170 may then be bonded to the conductive pads 132 or trace ends in therecesses 120 of interposer substrate 110 by, for example, reflowing theconductive bumps 166 and 176 (in the case of solder bumps) and/or curingthe conductive bumps 166 and 176 (in the case of conductive orconductor-filled polymer bumps) as known in the art. Other methods ofbonding known in the art may be utilized, such as ultrasonic or thermalcompression, with suitable conductive bump materials.

To assist in mounting and bonding the first and second semiconductordice 160 and 170 to the interposer substrate 110, a nonsolid conductivematerial in the form of a conductive paste 156 may be provided in therecesses 120 as depicted in FIGS. 2 and 3. Such conductive paste 156 maybe disposed in each of the recesses 120 by, for example, overlying thefirst and second surfaces 112 and 114 of interposer substrate 110 with astencil (not shown) patterned with openings corresponding with thepatterns of recesses and spreading the conductive paste 156 over thestencil to fill the recesses 120 in the interposer substrate 110 with aspread member (not shown). The conductive paste 156 may include, but isnot limited to, eutectic solder, conductive epoxy, or any conductivematerial known in the art. The recesses 120 may be partially orcompletely filled, as desired. Of course, the surfaces of interposersubstrate 110 having recesses 120 opening thereon may also merely befilled with conductive paste 156 and the excess removed, without the useof a stencil.

In another method, the conductive paste 156 may first be disposed on theconductive bumps 166 and 176 prior to assembling the respective firstand second semiconductor dice 160 and 170 to the interposer substrate110 by dipping the conductive bumps 166 and 176 in a pool of conductivepaste 156 or by depositing, dispensing or otherwise transferring theconductive paste to the conductive bumps 166 and 176. In still anotherapproach, conductive bumps such as bumps 166 or 176, unattached to asemiconductor die, may be disposed in the conductive paste 156 which isin the recesses 120 corresponding to a particular recess pattern. Asemiconductor die having a bond pad configuration with a substantiallymirror image of the particular recess pattern may then be aligned withand bonded to the conductive bumps.

If employed, the conductive paste 156 supplements the conductive bumps166 and 176 in electrical and mechanical interconnection between boththe first and second semiconductor dice 160 and 170 and the traces 130of interposer substrate 110. Further, the conductive paste 156 ensuresmechanical and electrical interconnection even if some of the conductivebumps 166 and 176 are inconsistent in height or the recesses 120 areinconsistent in depth, i.e., noncoplanar, wherein the conductive paste156 is disposed in the recesses 120 between the conductive pads 132 andthe conductive bumps 166 and 176. The conductive bumps 166 and 176 andthe conductive paste 156 may then be bonded to the conductive pads 132or trace ends in the recesses 120 of interposer substrate 110 aspreviously described.

It will be well appreciated by one skilled in the art that, since theconductive bumps 166 and 176 are substantially received within therecesses 120 of the interposer substrate 110 itself when bonded toconductive pads 132, the height of the semiconductor device assembly 180is minimized. Therefore, the conductive bumps 166 and 176 may be formedof a larger size than in conventional flip chip assemblies withoutincreasing the height of the flip chip semiconductor device assembly180, resulting in an increase of the electrical and mechanicalreliability and performance of the interconnections between theinterposer substrate 110 and the first and second semiconductor dice 160and 170. In addition, the first and second adhesive elements 152 and 154(if used) on the respective first and second surfaces 112 and 114 of theinterposer substrate 110 as well as the conductive paste 156 in therecesses 120 (if used) may compensate for any irregularities due tovarious conductive bump sizes, recess depths and planarity variation inthe surfaces of the interposer substrate 110 and the first semiconductordie 160 and second semiconductor die 170.

Further, the recesses 120 in the interposer substrate 110 provide aninherent improved alignment capability in comparison to a conventionalflip chip-type semiconductor device assembly because the conductivebumps 166 and 176 easily slide into their respective correspondingrecesses 120 to ensure proper alignment with conductive pads 132 andproper attachment of first and second semiconductor dice 160 and 170 tointerposer substrate 110. For example, the recesses 120 may be formed inthe interposer substrate 110 to be approximately 125 μm in diameter orwidth and the conductive bumps 166 formed on the semiconductor die 160may be about 75 μm in diameter or width. Thus, the dimensions of therecesses 120 accommodate inconsistencies in dimensions and locations ofthe conductive bumps 166 therein, facilitating die alignment.

As shown in FIG. 4, a dielectric encapsulation material 182 such as whatis commonly termed an “underfill” material) may be optionally appliedalong the periphery of the first semiconductor die 160 and the secondsemiconductor die 170 adjacent interposer substrate 110 to fill aroundthe conductive bumps 166 and 176, respectively. The method employed toapply the encapsulation material 182 is preferably by pressurizeddispensing from dispenser 184, but may include any method known in theart, such as gravity and vacuum-assisted dispensing. In this manner, theencapsulation material 182 may be applied to fill any gaps around theconductive bumps 166, 176 in recesses 120 and the area around first andsecond adhesive elements 152 and 154. Alternatively, a nonflow film or anonflow paste may be used as the dielectric encapsulation material 182.The nonflow material, which may comprise a thermoset or thermoplasticmaterial, is applied prior to assembly of the semiconductor dice to theinterposer substrate 110. The film or paste, or even a combination ofthe two forms, allows conductive bumps 166, 176 to penetratetherethrough and effect an electrical connection. Suitable nonconductivefilms include UF511 and UF527 from Hitachi Chemical, SemiconductorMaterial Division, Japan. The encapsulation material 182 may beself-curing through a chemical reaction, or a cure accelerated by heat,ultraviolet light or other radiation, or other suitable means in orderto form a solid mass in the recesses 120. Such encapsulation material182 provides enhanced mutual securement of the components ofsemiconductor device assembly 180, precludes shorting between conductiveelements thereof, and protects the conductive elements fromenvironmental elements, such as moisture and dust. Further, compared tounderfilling of conventional flip chip assemblies, underfilling of theflip chip semiconductor device assembly 180 of the present inventionrequires less time since the encapsulation material is only directed tofill any gaps around the conductive bumps 166, 176 in recesses 120 andthe area around adhesive elements 152 and 154.

FIG. 5 depicts testing the semiconductor device assembly 180 of thepresent invention and specifically testing for the electrical integrityof the interconnections between the interposer substrate 110 and therespective first semiconductor die 160 and second semiconductor die 170as well as functionality of the semiconductor device assembly 180 withtest pads 134 provided proximate a periphery 116 of the interposersubstrate 110. Such test pads 134 are interconnected with the firstsemiconductor die 160 and second semiconductor die 170 through thetraces 130, conductive pads 132 and respective conductive bumps 166, 176so that testing members 188 (one shown) such as test probes may beplaced on a surface of each test pad 134 and electrical tests performedby conventional test equipment associated therewith (not shown) todetermine proper interconnection of the semiconductor device assembly180. The test pads 134 may be placed on both the first surface 112 andsecond surface 114 of the interposer substrate 110 at the periphery 116thereof on a portion of the interposer substrate 110 which is “off-site”from where the first semiconductor die 160 and second semiconductor die170 are mounted on the interposer substrate 110. Such a test padconfiguration enables the sharing of test tooling and hence reducescost.

FIG. 6 depicts a flip chip semiconductor device assembly 180 of thepresent invention interconnected to terminal pads 194 of anothersubstrate 190, such as a circuit board, with conductive elements 192therebetween. The flip chip semiconductor device assembly 180 may alsobe stacked with one or more other superimposed semiconductor deviceassemblies 180 with conductive elements 192 therebetween, wherein thebottom semiconductor device assembly 180 may be interconnected toterminal pads 194 of substrate 190. Interconnection of the conductiveelements 192 to interposer substrates 110 may be provided by bonding tothe conductive pads 133 exposed on either the first or second surfaces112, 114 of the interposer substrate 110. The conductive elements 192may be bonded to the conductive pads 133 prior or subsequent todispensing the encapsulation material 182.

Once the conductive elements 192 are bonded to the interposer substrate110 and the encapsulation material 182 has been provided thereto,complete encapsulation of the flip chip semiconductor device assembly180 may be effected, as depicted in FIGS. 7 and 8. In particular, firstsemiconductor die 160 and second semiconductor die 170 may then beeither partially or fully encapsulated by an encapsulation member 186with an encapsulation material 182. In the case of partiallyencapsulating the first semiconductor die 160 and second semiconductordie 170, an encapsulation material 182 may be dispensed by dispenser 184about the periphery thereof so that the back surfaces 164, 174 of thefirst semiconductor die 160 and second semiconductor die 170 are leftexposed. In the case of fully encapsulating the dice, encapsulationmaterial 182 may be provided by dispensing, spin-coating, glob-topping,transfer molding, pot molding or any suitable method known in the art.It is preferred that such encapsulation material 182 be applied to theback surfaces 164 and 174 of the respective first semiconductor die 160and the second semiconductor die 170 (which may be provided at the waferlevel) prior to dispensing encapsulation material 182 about theperiphery of first semiconductor die 160 and the second semiconductordie 170 in order to facilitate fully encapsulating each of the dice inthe semiconductor device assembly 180.

FIGS. 9 and 10 depict a second embodiment of the interposer substrate210 of the present invention, wherein FIG. 9 illustrates a top plan viewof a first recess pattern 222 and a second, different recess pattern 224and FIG. 10 illustrates a cross-sectional side view of the interposersubstrate 210 taken along line 10-10 in FIG. 9. As in the firstembodiment, interposer substrate 210 includes a first surface 212 and asecond surface 214, an adhesive 252 provided on a die attach site 242 onthe first surface 212 and traces 230 extending from the bottoms ofmultiple recesses 220 to test pads 234 on the interposer substrate 210.As such, the second embodiment is substantially similar to the firstembodiment in many respects, except the interposer substrate 210 of thesecond embodiment includes both a first recess pattern 222 and a secondrecess pattern 224 formed in the first surface 212 of the interposersubstrate 210. It should be noted that a recess 220 of the first recesspattern 222 and a recess 220 of the second recess pattern 224 eachexpose a portion of a common conductive trace extending peripherallyoutward from a recess 220 of first recess pattern 222 and past a recess220 of second recess pattern 224 to a test pad 234.

As depicted in FIG. 10, conductive paste 256 may be provided in therecesses 220, after which a semiconductor die 260 may be mounted andbonded to the interposer substrate 210 as shown in FIG. 11 to provide aflip chip semiconductor device assembly 280 of the present invention. Asin the first embodiment, encapsulation material may also be dispensedalong a periphery of the semiconductor die 260 to fill the space aroundand proximate the conductive bumps 266. Further, testing members 188 mayalso be used to test the electrical integrity and functionality of theflip chip semiconductor device assembly 280 by placing the testingmembers 188 directly on the test pads 234 exposed proximate a periphery216 on the first surface 212 of the interposer substrate 210. Such alocale for testing pads provides easy access and reduces the cost fortesting.

According to the present invention, the first and second recess patterns222 and 224 in the first surface 212 of the interposer substrate 210provide versatility in that semiconductor dice of different sizes and/ordifferent bumped configurations may optionally be mounted to the firstsurface of the interposer substrate. Such versatility provides that thefirst recess pattern 222 and the second recess pattern 224 share acommon die attach site, namely, die attach site 242, optionally bearingan adhesive element 252. Further, as in the first embodiment, therecesses 220 are sized and configured to substantially completelyreceive the conductive bumps 266 of the semiconductor die 260 so thatthe active surface 262 of the die 260 lies immediately adjacent thefirst surface 212 of the interposer substrate 210. As such, thesemiconductor device assembly 280 of the present invention provides areduced height compared to conventional flip chip assemblies.

FIG. 12 depicts the semiconductor device assembly 280 of the secondembodiment stacked with one or more other assemblies 280, wherein thebottom assembly 280 is interconnected to a substrate 290 with conductiveelements 292 therebetween. The one or more other assemblies 280 mayinclude a semiconductor die 260 with a bumped configuration to fiteither the first recess pattern and/or the second recess pattern. Assuch, the first and second recess patterns 222 and 224 on the firstsurface 212 of the interposer substrate 210 provide optional attachmentof differently sized semiconductor dice and/or semiconductor dice withdifferently sized and configured recess patterns for mounting to acommon die attach site 242 on the interposer substrate 210.

As in the first embodiment, the semiconductor device assembly 280attached by conductive elements 292 to the terminal pads 294 ofsubstrate 290, either stacked with other assemblies 280 or individuallyon the substrate 290, may then be either fully encapsulated or partiallyencapsulated by an encapsulation member 186 and/or by a dispenser 184,as previously described in FIGS. 7 and 8.

FIG. 13 depicts a top plan view of a third embodiment of the interposersubstrate 310 of the present invention. As in the first embodiment,interposer substrate 310 includes a first surface 312 and a secondsurface 314 with a respective first adhesive element 352 and a secondadhesive element 354 thereon, and traces 330 extending from multiplerecesses 320 to testing pads 334 exposed on first and second surfaces312 and 314 of the interposer substrate 310. Each adhesive element 352and 354 is provided on a first die attach site 342 and a second dieattach site 344 on respective first and second surfaces 312 and 314 ofinterposer substrate 310. As such, the third embodiment is also similarto the first embodiment in many respects, except the interposersubstrate 310 of the third embodiment includes both a first recesspattern 322 and a second recess pattern 326 in the first surface 312 ofthe interposer substrate 310 and a third recess pattern 324 and a fourthrecess pattern 328 in the second surface 314 of the interposer substrate310. Further, a first adhesive element 352 and a second adhesive element354 (under first adhesive element 352) are disposed on a center portionof respective first surface 312 and second surface 314 or anotherportion on the first and second surfaces 312 and 314 unoccupied byrecesses 120.

As depicted in FIG. 13, the recesses 320 in the first recess pattern 322and the second recess pattern 326 may be staggered with respect to therecesses in the third recess pattern 324 and the fourth recess pattern328. Further, the recesses 320 in the first recess pattern 322 may berelatively more inwardly disposed with respect to the recesses 320 inthe second recess pattern 326. Likewise, the recesses 320 in the thirdrecess pattern 324 may be relatively more inwardly disposed with respectto the recesses 320 in the fourth recess pattern 328. With thisarrangement, interposer substrate 310 provides versatility to mountdifferently sized dice in a stacked arrangement on a single interposersubstrate 310. That is, the interposer substrate 310 of the presentinvention provides that variously sized semiconductor dice and/orsemiconductor dice having different conductive bump configurations maybe optionally mounted on both the first surface 312 and the secondsurface 314 of the interposer substrate 310. Further, such optionalmounting of semiconductor dice provides that the first recess pattern322 and second recess pattern 326 share a common die attach site,namely, die attach site 342 as well as common conductive traces 330extending to a set of test pads 334. Likewise, the third recess pattern324 and the fourth recess pattern 328 also share a common die attachsite, specifically, die attach site 344 as well as common conductivetraces 330 extending to a set of test pads 334. The mounting and bondingof the first and second dice may be effected as previously describedwith respect to the first and second embodiments of the presentinvention.

Further, as in the previous embodiments and as noted above, interposersubstrate 310 includes test pads 334 fanned out from recesses 320proximate a periphery 316 of interposer substrate 310 and exposed on thefirst surface 312 and/or the second surface 314 of interposer substrate310. As such, subsequent to mounting semiconductor dice to interposersubstrate 310 on the first surface 312 and/or the second surface 314thereof, the resulting flip chip semiconductor device assembly may betested to determine the mechanical and electrical integrity of theinterconnections between the semiconductor dice and the interposersubstrate 310.

FIG. 14 depicts a top plan view of a fourth embodiment of the interposersubstrate 410 of the present invention. As in the first embodiment,interposer substrate 410 includes a first surface 412 and a secondsurface 414 with an adhesive element 452 on the first surface 412, andtraces 430 extending from multiple recesses 420 to testing pads 434exposed on the first surface 412 of the interposer substrate 410. Assuch, the fourth embodiment is similar to the first embodiment in manyrespects, except the interposer substrate 410 of the fourth embodimentincludes a first recess pattern 422, a second recess pattern 426, athird recess pattern 424 and a fourth recess pattern 428, each formed inthe first surface 412 of the interposer substrate 410.

As depicted in FIG. 14, the recesses 420 in the first recess pattern 422and the second recess pattern 426 may be staggered with respect to therecesses 420 in the third recess pattern 424 and the fourth recesspattern 428. Further, the recesses 420 in the first recess pattern 422may be inwardly located with respect to the recesses in the secondrecess pattern 426, opening onto the same conductive traces 430.Likewise, the recesses 420 in the third recess pattern 424 may beinwardly aligned with respect to the recesses in the fourth recesspattern 428, opening onto the same conductive traces 430. With thisarrangement, interposer substrate 410 provides versatility to mountdifferently sized dice thereon. That is, interposer substrate 410provides versatility in that variously sized semiconductor dice and/orsemiconductor dice having different conductive bump configurations maybe optionally mounted on the first surface 412 of interposer substrate410, wherein each recess pattern includes a common die attach site 442.The mounting of the semiconductor die may be employed as previouslydescribed with respect to the first and second embodiments of thepresent invention.

Further, as in the previous embodiments, interposer substrate 410includes test pads 434 fanned out from recesses 420 proximate aperiphery 416 of interposer substrate 410 and exposed on the firstsurface 412 of interposer substrate 410. Test pads 434 are each commonto two recess patterns, as shown in FIG. 14. As such, subsequent tomounting semiconductor dice to the first surface 412 of interposersubstrate 410, the resulting flip chip semiconductor device assembly maybe tested to ensure that electrical interconnection has beensuccessfully made and satisfactory functionality is exhibited, asdescribed previously with respect to the first and second embodiments.

Similar to that described in each of the previous embodiments, theinterposer substrate of the present invention may also be assembled at awafer level, wherein the interposer substrate is a wafer scaleinterposer substrate including at least two different recess patterns.As such, the wafer scale interposer substrate may facilitate assemblywith different wafers having different bumped configurations whichcorrespond with the at least two different recess patterns in the waferscale interposer substrate. In this manner, optional wafers withdifferent bumped configurations may be attached face (active surface)down to the wafer scale interposer substrate with conductive bumps onthe wafer disposed and substantially received in recesses formed in theinterposer substrate. The wafer and interposer substrate may then besingulated or diced into individual semiconductor assemblies. Partialencapsulation of the semiconductor dice on the wafer or wafers may beperformed at the wafer level and completed subsequent to being dicedinto individual flip chip semiconductor device assemblies according tothe present invention.

As illustrated in block diagram form in FIG. 15, an exemplary flip chipsemiconductor device assembly 580 of the present invention, aspreviously described herein with respect to various embodiments, ismounted to a circuit board 590, such as previously discussed substrate190, in an electronic system, such as a computer system 502. In thecomputer system 502, the circuit board 590 is connected to a processordevice 504 which communicates with an input device 506 and an outputdevice 508. The input device 506 may include a keyboard, mouse,joystick, cell phone, PDA system, or any other electronic input device.The output device 508 may include a monitor, a printer, a storagedevice, such as a disk drive, a cell phone, a PDA system, or any otherelectronic output device. The processor device 504 may be, but is notlimited to, a microprocessor or a circuit card including hardware forprocessing computer instructions. Additional structure for an electronicsystem, such as a computer system 502, would be readily apparent tothose skilled in the art.

Yet another embodiment of the present invention is depicted in FIG. 16of the drawings. Interposer substrate 610 is comprised of a singleconductive layer sandwiched between two dielectric members 636. Theconductive layer may be patterned into a plurality of conductive traces630 including conductive pads 632, which may comprise trace ends,exposed through a plurality of recesses 620 formed through bothdielectric members 636. It is contemplated that the conductive layer maybe provided as a sheet or film of copper adhered to one dielectricmember 636 and conductive traces 630 formed by etching the copper,subsequent to which a second dielectric member is superimposed on theconductive traces, although the invention is not so limited. Recesses620 may be preformed in one or both dielectric members 636, or formed inone or both dielectric members 636 after the laminated structure ofinterposer substrate 610 is formed.

As also depicted in FIG. 16, a first semiconductor die 660 and a secondsemiconductor die 760 are respectively connected to conductive traces630 by conductive bumps 666 and 676, which extend into recesses 620 tocontact conductive pads 632. A conductive paste (not shown) may bedisposed in recesses 620 or conductive bumps 666 and 676 dipped thereinto enhance the connections between conductive bumps 666, 676 and theconductive pads 632 at the bottoms of recesses 620, as previouslydiscussed with respect to other embodiments. Furthermore, semiconductordice 660 and 670 may be respectively adhered to exterior surfaces ofinterposer substrate 610 by adhesive elements 652 and 654, again aspreviously discussed. If desired, a dielectric encapsulant material 682,which may be any previously disclosed herein or otherwise suitable foruse, may be introduced between each semiconductor die 660, 670 and itsadjacent dielectric member 636 to fill the standoff area therebetween aswell as any portions of recesses 620 unfilled by conductive bumps 666and 676. Further, and if desired, semiconductor dice 660 and 670 may beencapsulated about their peripheries and back sides as shown in brokenlines to provide a fully encapsulated package 680. As with otherembodiments, enlarged conductive bumps may be formed at appropriatelocations on one or both sides of interposer substrate 610 through otherrecesses in a dielectric member 636 for connection of the semiconductordevice package 680 to other packages or to a carrier substrate (notshown).

In lieu of stacking semiconductor packages 680, however, it iscontemplated that either approach to the present invention, comprising aflexible interposer substrate using dual conductive layers having adielectric member interposed therebetween or a single conductive layerinterposed between two dielectric members, may be employed to implementa folded interposer substrate package according to the presentinvention. An exemplary embodiment of a dual-sided folded interposersubstrate package is disclosed in FIG. 17.

FIG. 17 depicts an interposer substrate 710, which may comprise either adual conductive layer or single conductive layer interposer substrateaccording to the present invention, folded over upon itself in twoportions 710 a and 710 b, with back-to-back semiconductor dice 760 a and760 b therebetween and a third semiconductor die 760 c on portion 710 a.All three semiconductor dice 760 a-c are flip-chip configured withconductive bumps 766 projecting therefrom into recesses (not shown forclarity) in interposer substrate 710 as discussed with respect toprevious embodiments. The standoff areas between each semiconductor dice760 a-c and its adjacent portion of interposer substrate 710 may befilled with an encapsulant material 782, as may the peripheries and backsides of the semiconductor dice 760 a-c and the bight area 790 of thefold between interposer substrate portions 710 a and 710 b. Enlargedconductive elements 792 may be employed to connect the interposersubstrate 710 to higher-level packaging, such as a carrier substrate inthe form of a printed circuit board. Exemplary folded interposersubstrate package 780 a results. Folded interposer substrate package 780a may be formed by respectively connecting semiconductor dice 760 a and760 b to the same side of interposer substrate 710 in unfolded or planarform over then-laterally adjacent portions 710 a and 710 b, then foldingthe substrate 710 and adhering semiconductor dice 760 a and 760 bback-to-back, after which semiconductor die 760 c is connected tointerposer substrate portion 710 a and encapsulation and bumping withenlarged conductive elements may be completed. Semiconductor dice 760a-c may be of the same type or origin or of different types or origin,as desired, and perform the same or different functions.

While the present invention has been disclosed in terms of certainexemplary embodiments and variations thereof, those of ordinary skill inthe art will recognize and appreciate that the invention is not solimited. Additions, deletions and modifications to the disclosedembodiments may be effected without departing from the scope of theinvention as claimed herein. Similarly, features from one embodiment maybe combined with those of another while remaining within the scope ofthe invention. For example, features of the fourth embodiment may becombined with the second embodiment, wherein the first surface of theinterposer substrate may include four recess patterns and the secondsurface of the interposer substrate may include two recess patterns.Further, any number of recess patterns may be provided on the firstsurface and/or the second surface of the interposer substrate foroptional semiconductor die attachment thereto.

1. A method of assembling a semiconductor assembly, the methodcomprising: providing at least one semiconductor die having an activesurface and a back surface, the active surface having a plurality ofconductive bumps projecting therefrom; providing an interposer substratehaving a first surface and a second surface and comprising a dielectricmember having at least one conductive layer thereon including aplurality of conductive traces, the interposer substrate having aplurality of recesses formed in at least one of the first and secondsurfaces and exposing at a bottom thereof at least a portion of one ofthe conductive traces, the recesses arranged in at least a first recesspattern and a second, different recess pattern; and disposing theplurality of conductive bumps of the at least one semiconductor die inat least one of the at least the first recess pattern and the secondrecess pattern so that the active surface of the at least onesemiconductor die lies adjacent at least one of the first surface andthe second surface of the interposer substrate.
 2. The method of claim1, wherein providing the interposer substrate comprises providing theinterposer substrate with the first surface including both the at leastthe first recess pattern and the second recess pattern.
 3. The method ofclaim 2, wherein disposing further comprises matching a configuration ofconductive bumps of the at least one semiconductor die to one of the atleast the first recess pattern and the second recess pattern.
 4. Themethod of claim 3, wherein disposing comprises mounting the at least onesemiconductor die over one of the at least the first recess pattern andthe second recess pattern on a first die attach site commonly shared bythe at least the first recess pattern and the second recess pattern. 5.The method of claim 2, wherein providing the interposer substratecomprises providing the interposer substrate with the second surfacethereof including at least a third recess pattern and a fourth recesspattern.
 6. The method of claim 5, wherein disposing comprises matchinga configuration of conductive bumps of the at least one semiconductordie to at least one of the at least the third recess pattern and thefourth recess pattern.
 7. The method of claim 6, wherein disposingcomprises mounting the at least one semiconductor die over the at leastone of the at least third pattern and the fourth recess pattern on asecond die attach site commonly shared by the at least third recesspattern and the fourth recess pattern.
 8. The method of claim 2, whereinproviding the interposer substrate comprises providing the interposersubstrate with the first surface thereof including at least a thirdrecess pattern and a fourth recess pattern.
 9. The method of claim 8,wherein disposing comprises matching a configuration of conductive bumpsof the at least one semiconductor die to at least one of the at leastfirst recess pattern, the second recess pattern, the at least thirdrecess pattern and the fourth recess pattern.
 10. The method of claim 9,wherein disposing comprises mounting the at least one semiconductor dieover the at least one of the at least the first recess pattern, thesecond recess pattern, the at least the third recess pattern and thefourth recess pattern on a first die attach site commonly shared by eachof the at least the first recess pattern, the second recess pattern, thethird at least the recess pattern and the fourth recess pattern.
 11. Themethod of claim 1, wherein disposing comprises attaching the activesurface of the at least one semiconductor die to an adhesive element ona die attach site on at least one of the first surface and the secondsurface of the interposer substrate.
 12. The method of claim 1, furthercomprising electrically testing at least interconnections between the atleast one semiconductor die and the conductive traces of the interposersubstrate by positioning a testing member on test pads conductivelyconnected to the conductive traces and exposed on at least one of thefirst surface and the second surface proximate a periphery of theinterposer substrate.
 13. The method of claim 1, further comprisingdispensing encapsulation material proximate the conductive bumps in aspace defined between the active surface of the at least onesemiconductor die and the at least one of the first surface and thesecond surface of the interposer substrate.
 14. The method of claim 1,further comprising at least partially encapsulating the at least onesemiconductor die and the interposer substrate with encapsulationmaterial.
 15. The method of claim 1, further comprising mounting thesecond surface of the interposer substrate to another substrate withconductive elements disposed therebetween.
 16. A method of fabricating asubstrate for mounting at least one semiconductor die in a flip chiparrangement thereto, the method comprising: providing an interposersubstrate having a first surface and a second surface and a dielectricmember having at least one conductive layer thereon including aplurality of conductive traces; forming a plurality of recesses in atleast one of the first surface and the second surface of the interposersubstrate arranged in a first recess pattern and a second, differentrecess pattern to expose at least portions of the conductive traces atrecess bottoms and to a depth into the interposer substrate sufficientto substantially receive therein conductive bumps on an active surfaceof the at least one semiconductor die.
 17. The method of claim 16,wherein forming comprises sizing the recesses so that the conductivebumps on the at least one semiconductor die are receivable therein suchthat an active surface of the at least one semiconductor die liesadjacent the at least one of the first surface and the second surface ofthe interposer substrate.
 18. The method of claim 16, wherein formingcomprises forming the first recess pattern and the second recess patternin the first surface of the interposer substrate so that each of thefirst recess pattern and the second recess pattern share a common firstdie attach site for mounting the at least one semiconductor die thereto.19. The method of claim 18, wherein forming comprises forming therecesses of the first and second recess patterns so that each recess ofthe first recess pattern exposes at least a portion of a conductivetrace exposed by a recess of the second recess pattern and placing eachrecess of the first recess pattern relatively outwardly with respect tothe recess of the second recess pattern exposing at least a portion ofthe same conductive trace.
 20. The method of claim 18, wherein formingfurther comprises forming a third recess pattern and a fourth recesspattern in the second surface of the interposer substrate so that eachof the third recess pattern and the fourth recess pattern share a commonsecond die attach site for mounting the at least one semiconductor diethereto.
 21. The method of claim 20, wherein forming comprises formingrecesses of the third and fourth recess patterns so that each recess ofthe third recess pattern exposes at least a portion of a conductivetrace exposed by a recess of the fourth recess pattern and placing eachrecess of the third recess pattern relatively outwardly with respect tothe recess of the fourth recess pattern exposing at least a portion ofthe same conductive trace.
 22. The method of claim 20, wherein formingcomprises staggering the recesses of the third recess pattern and thefourth recess pattern with respect to the recesses of the first recesspattern and the second recess pattern.
 23. The method of claim 18,wherein forming further comprises forming at least a third recesspattern in the first surface of the interposer substrate so that each ofthe first recess pattern, the second recess pattern and the at least thethird recess pattern share the common first die attach site for mountingthe at least one semiconductor die thereto.
 24. The method of claim 18,wherein forming further comprises forming a third recess pattern and afourth recess pattern in the first surface of the interposer substrateso that each of the first recess pattern, the second recess pattern, thethird recess pattern and the fourth recess pattern share the commonfirst die attach site for mounting the at least one semiconductor diethereto.
 25. The method of claim 16, further comprising forming anadhesive element on a die attach site on the at least one of the firstsurface and the second surface of the interposer substrate.
 26. Themethod of claim 16, further comprising forming test pads proximate aperiphery of the interposer substrate and exposed on the at least one ofthe first surface and the second surface of the interposer substrate sothat each test pad is in communication with one of the conductivetraces.